Analytics and optimization
System designers can use Tessent’s SoC monitoring and analytics features to refine performance based on the in-silicon behavior of their SoCs.
All too often, the real-world performance seen when first silicon arrives from the fab does not meet the full expectations of the silicon architect. Perhaps the chip is functionally free from bugs, but cannot attain the maximum designed-for data rate; or it may “run a little hot” – the power consumption figures are within the design limits, but higher than the ideal.
Tessent can help in this situation. By integrating fit-for-purpose non-intrusive monitoring and profiling blocks into the hardware design, the engineering team can obtain actionable intelligence from the real silicon, that they can use to tune performance parameters. For example, such information might show that it is possible to slow down or turn off a particular functional block without impacting performance.
We also assist the software team, who get to see logic-analyzer-like traces created by their software running on real silicon – a prime opportunity to refine and produce better code.
Making design decisions based on real data can help during the silicon bring up and post-silicon validation phases. And it can help the architecture team as they start work on the next generation of devices, providing known-good input for simulations, and guiding the team towards promising avenues for performance enhancement, power saving and cost reduction / value engineering.
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