SoC Debug

The average SoC now has more than 100 IP blocks. Such devices are powerful, but there is a problem: they are so complex that it is effectively impossible to understand how they operate in every circumstance. This poses a problem for silicon architects, debug engineers, the SoC bring-up team and the software engineers.

Debug, for example, currently has a high profile. It consumes up to one third of the design effort required to create a complex heterogeneous SoC.

Tessent Embedded Analytics solves all of these problems by providing a holistic, vendor-independent view of a device’s operation – and it does all of this at wire speed and non-intrusively. The gains from our technology can be dramatic – up to two months shaved off an 18-month development cycle, equating to cost savings running into the millions of dollars.

We give you full visibility of code, with the trace, cross-point, breakpoints and triggers that you would expect from an advanced debug solution.

Tessent Embedded Analytics can be used standalone, or as an adjunct to vendor-specific debug solutions (for example Arm CoreSight): we support a variety of CPU/GPU architectures, including Arm, MIPS, CEVA and Cadence Tensilica.

UltraDebug can use standard debug ports, but also incorporates patented technology that allows a single high-speed chip interface such as USB to be used simultaneously for both system communication and for debugging. This removes the necessity to provide dedicated debug pins on the device, and allows much faster data transfer than is possible with a traditional serial interface such as JTAG.

You can find out more about our IP modules for SoC monitoring and analytics here.