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Bristol RISC-V Meetup
30 April 2019 @ 6:00 pm-8:30 pm
Following our successful first RISC-V Meetup in Bristol last October, we are pleased to invite you to join us at our second one on Tuesday 30 April, which will be hosted by UltraSoC and Imperas Software!
The evening will start at 6pm with a networking session, including refreshments. We will have a number of interesting speakers, and there will also be live technical demonstrations.
Please click here to book your place.
This Meetup will take place in the events room on the 4th floor of DeskLodge at Temple Way, a short walk from Bristol Temple Meads station.
Speakers will include:
- Professor David May – University of Bristol
- Dr Carl Shaw – Cerberus Laboratories, Co-Founder
- Dave McEwan – EPSRC Centre for Doctoral Training in Communications, PhD student
- Mark Hill – Huawei, Chief CPU Architect
- Simon Davidmann – Imperas Software, Founder and CEO
- Gajinder Panesar – UltraSoC, CTO
- Ben Marshall – University of Bristol, Research Associate
Places are limited, so please book soon! We look forward to seeing you there.
Please visit https://riscv.org/ for more information about RISC-V, and to read how, as a member of the RISC-V Foundation, UltraSoC is deeply involved in developing and defining the debug architecture for RISC-V standards, visit https://www.tessentembeddedanalytics.com/technology-2/risc-v/. Imperas helps RISC-V developers with virtual platforms and tools for early software development, RISC-V compliance testing and test development. Visit http://www.imperas.com/imperas-riscv-solutions.
You may like to check out our blog post from our first Bristol RISC-V Meetup: ‘The rising temperature of RISC-V in Bristol‘.
Also, if you are interested in speaking at a forthcoming RISC-V Meetup, please do get in touch by sending an email to email@example.com. This community is to provide an open platform for all in which to share experiences, to build understanding and open doors to opportunities based on the RISC-V architecture.