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DFT India Tech Day

10 November 2020

We are looking forward to DFT India Tech Day, which is taking place online on 10 November 2020, 9.30am to 1pm Asia/Kolkata (4am to 7.30am GMT).

*For those that cannot join this event live, please still register and recordings of the sessions will be shared with you afterwards.

Presenters:

Aileen Ryan – Senior Director of Portfolio Strategy at Mentor, a Siemens Business
Lee Harrison – Automotive IC Test Solutions Manager at Mentor, A Siemens Business
Ron Press – Technology Enablement Director of the Tessent product family at Mentor, A Siemens Business

Click to find out more and to book your place

Overview

The half day seminar will focus on following key test challenges IC vendors face as they involve in enabling high test quality on complex application specific designs.
  • Design augmentation to detect, mitigate and eliminate security, functional safety, device early failure and wear-out risks
  • Effective use of realistic fault modeling to gather precise information on defect distribution and detection
  • Meeting high automotive test coverage goals within expected time budgets
  • Extracting value from Tessent Connect platform to achieve high implementation efficiency
  • DFT Tips and Tricks
  • Customer Experiences

What you will learn

This half-day seminar will focus on key test challenges IC vendors face as they try to make the promises of the autonomous age a reality.

The world of ATPG just changed with the introduction of a new solution that can calculate the critical-area effectiveness of each test pattern. Knowing the likelihood of detecting defects based on their critical area, combined with pattern sorting between various pattern sets, lets users choose the most effective test patterns to apply.

The growth of electronics in automobiles has spurred significant innovation in the development of advanced safety mechanisms for all the electrical and electronic systems in a vehicle. In addition to very high-quality manufacturing test, ICs for safety-critical applications need in-system test to detect faults and monitor circuit aging. Scan-based logic built-in-self-test (LBIST) is the technique used for in-system test, but traditional LBIST often can’t meet the coverage goals within the required diagnostic test time interval (DTTI). This talk will look at the current challenges and introduce new DFT technique to the overcome the problem.

EDA companies used to supply discrete DFT tools for ATPG, or memory BIST, or other functions.  Semiconductor DFT teams have traditionally been developed with the overall device in mind and were responsible for the SoC level integration. This is no longer possible. DFT for modern SoCs requires methodologies to address design scaling with plug-and-play principles and automation.  The Tessent platform was developed over many years to solve these issues by providing one common tool and common database which includes various DFT functions such as ATPG or BIST as well as top level and hierarchical integration.  As a result, users can achieve a demanding schedule with automation and hierarchical/SoC level integration.  The DFT methodologies described here are designed to address continued design scaling with plug-and-play principles and automation.

Click to find out more and to book your place

Details

Date:
10 November 2020
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