27 October 2020-28 October 2020
We are looking forward to participating in DVCon Europe, which is taking place online on 27 – 28 October 2020.
Gajinder Panesar, Fellow, Mentor, A Siemens Business, will participate in a panel session on Day Two:
‘Verification Challenges of an Exascale Supercomputer’.
Moderator: Jean-Marie Brunet – Mentor, A Siemens Business.
Chip design and verification experts from Europe and the U.S. will join moderator Jean-Marie Brunet from Mentor, a Siemens Business, for a discussion about the verification requirements of a new type of exascale supercomputer. At the end of the panel, they will attempt to define a specialized new verification flow to support the initiative.
Europe and the European Processor Initiative (EPI) consortium are taking a huge leap forward with the goal to design a low-power, high-performance exascale supercomputer. Many notable European companies are committed to a revolutionary new microprocessor architecture and roadmap for a well-implemented design.
The stakes are high. A secure and reliable microprocessor to support high-performance computing will need to meet the demands of a range of emerging complex applications. Those include artificial intelligence, connected mobility, storage, research, health, weather forecasting, energy, defense, chemicals, engineering, cybersecurity and smart cities as a start.
Achieving success will not be possible without robust verification. A new exascale supercomputer design creates far-reaching implications and potential consequences for today’s design verification flow that could require reimagining and overhauling each product segment. It may mean reeducation of verification engineers as well.
To find out more, please visit the event website.