UltraSoC exhibited at Embedded World 2018 as part of the RISC-V pavilion, Booth 3A-419

On the RISC-V Pavilion at Embedded World, UltraSoC was very busy talking with delegates about its deep involvement in developing and defining the debug architecture for RISC-V standards. 

That involvement includes UltraSoC and Lauterbach’s recent announcement about their extended collaboratively delivered universal SoC (system on chip) development and debug environment with the addition of support for the RISC-V open-source processor architecture.

On the opening morning of the show there was a full day RISC-V track, and UltraSoC CEO Rupert Baines and Russ Klein of Mentor Graphics gave a presentation on: ‘RISC-V: Emulation and Rich, Non-Intrusive Analytics Address Verification Complexity’ that explained how embedded analytics can be combined with advanced emulation technology such as Mentor’s VELOCE, to provide a development flow that combines the previously disparate pre- and post-silicon domains.

More details of the full schedule for the RISC-V Class can be seen here on the RISC-V website.

Click here to hear UltraSoC CEO Rupert Baines report from the show