UltraSoC were pleased to exhibit on the RISC-V Foundation Pavilion at Embedded World 2019, from 26th to 28th February 2019 in Nuremberg.

During the event, UltraSoC talked with delegates about its deep involvement in developing and defining the debug architecture for RISC-V standards. We also had an exciting announcement about the expansion of our embedded analytics architecture to help designers of heterogeneous multicore SoCs – and in particular those aimed at emerging AI and ML applications.  And we demonstrated our recently announced UltraDevelop 2 integrated development environment for the first time at a public event.

As well as presentations on the booth, as part of the main event program UltraSoC CEO Rupert Baines presented in the RISC-V session on ‘Embracing a System Level Approach: Combining Arm and RISC-V in Heterogeneous Designs’ on Tuesday 26 February at 4.30pm.

In a video interview with Rick O’Connor of the RISC-V Foundation, UltraSoC CEO Rupert Baines spoke about UltraSoC’s new UltraDevelop 2 integrated development environment, and our work with Western Digital on development tools for the SweRV CPU architecture.

Also have a read of our event round-up blog: ‘Embedded World: It’s not MWC, but its so much more than that‘ by UltraSoC Marketing Manager Jo Windel.