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Webinar – Andes, Imperas and UltraSoC: Optimizing embedded RISC-V hardware/software development

15 July 2020 @ 8:00 am-9:00 am

Optimizing embedded RISC-V hardware/software development from virtual models to in-life silicon instrumentation

Join this webinar with Andes, Imperas, and UltraSoC on the use of virtual platforms and FPGA’s for RISC-V multicore SoCs as early development platforms and software driven hardware verification and analysis.

Click here to register your place

Part 1 (click here to watch) of our webinar series focused on architecture. We are excited for Part 2, where our technology ecosystem will focus on hardware and software implementation. (And stay tuned for Part 3, coming soon!).

⏰ As previously, we will be running the webinars twice; on 15 July 2020, at 8am PDT (4pm BST, 5pm CET, 11pm CST) and 5pm PDT (1am BST, 8am CST on 1 July). Registering will allow you to join at both times. However, it would be helpful if you could indicate by checking one of the boxes below which webinar you intend to join.

The Agenda will cover the key prototype phases of SoC design:

  • Virtual platforms as early evaluation & demo ‘boards’ – Early software development including debug and verification
  • Processor cores implemented as FPGA prototypes – Optimized features for Cores and Processor sub-systems
  • Advanced analytics with FPGA prototypes – Debug & Trace, and On-Chip performance monitors and analytics

The webinar will conclude with a hosted Q&A session with the presenters as a group discussion.

Unable to join on the day? Please still register, and you will be sent a recording of the webinar when it is available.