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RISC-V Summit 2019
09 December 2019-12 December 2019
UltraSoC demonstrated its embedded analytics technology at the 2nd RISC-V Summit 2019 in San Jose, from 9 – 12 December. Following hot on the heels of our announcement that we have joined the OpenHW Group, we’ve just announced some exciting news about our RISC-V trace solutions. And on the UltraSoC booth we demonstrated new high-speed interfacing options that enable SoC designers to access detailed data on the behavior of their chips – both in the lab and after deployment in the field.
UltraSoC CTO Gajinder Panesar and VP Engineering Iain Robertson presented in the main program on ‘Every CPU Cycle Counts’. Also CEO Rupert Baines presented on the Western Digital booth, and Gajinder participated in a Processor IP Showcase panel session.