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RISC-V Summit 2020

08 December 2020-10 December 2020

RISC-V Summit

Join Tessent Embedded Analytics and our colleagues from the Mentor embedded software team at this year’s RISC-V Summit 2020, which is taking place online from 8th to 10th December 2020. We’ll be showcasing an online booth where you can interact with our technical experts, find out more about our solutions, and see a demonstration of our on-chip functional monitoring and analytics technology. We also have two talks in the main (online) conference:

Mentor Fellow, Gajinder Panesar, and President at Picocom, Peter Claydon
RISC-V in 5G New Radio Small Cell Base Stations
Wednesday 9 December | Time: 13:30pm – 13:50pm PDT | Hardware Cores / SoCs session

Mentor Technical Director, Russ Klein, and Mentor Embedded Software Technologist, Colin Walls
Embedded Software Reimagined: Thread Processors Implemented Using RISC-V
Thursday 10 December | Time: 10:15am – 11:45am PDT | System Architecture session

If you would like to arrange to connect with us during the event, please email jo_windel@mentor.com who would be pleased to arrange this.

Please visit the event website for more information and to register your place, using the code ‘MENTOR’ for a 25% discount.



08 December 2020
10 December 2020
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