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RISC-V Summit

03 December 2018-06 December 2018

We’re excited to be sponsoring the first RISC-V Summit in Santa Clara (Dec 3-6). We’ll be demonstrating the industry’s only commercial debug and trace solution for RISC-V – as well as showing exciting developments that bring the potential of the RISC-V architecture to automotive designers.

At this event leaders in the ecosystem will share live product demos and future plans for RISC-V technology, allowing delegates to explore the latest innovations on the market. There will be three full days of presentations and updates on the RISC-V architecture, commercial and open-source implementations, software and silicon, vectors and security, applications and accelerators, simulation infrastructure and much more.

UltraSoC CTO Gajinder Panesar will use his conference presentation to call upon the growing RISC-V community to embrace a truly open and flexible approach, in which a multiplicity of different processor architectures will need to co-exist and interwork.

As part of our growing involvement in the automotive functional safety and security sector, on Tuesday 4th December Gadge will be presenting with ResilTech Senior Safety Engineer Marco Demi on ‘Functional Safety and Security, ISO26262 and their Implications for the RISC-V Ecosystem’.

On the same day, Gajinder will also present on ‘Embracing a System-Level Approach in the Real World: Combining Arm and RISC-V in a Heterogeneous Designs’.

We’re delighted to be able to offer a 25% discounted Conference pass (enter VIP code USRISCV25 at check-out).

If you’d prefer to just visit the expo hall, a limited number of free expo passes are still available. Visit the registration page and enter code RVS18UTS.

To arrange to meet with the UltraSoC team during the event, please email jo.windel@ultrasoc.com who would be pleased to arrange this.

To find out more about the event and to register your place, please visit the event website.


03 December 2018
06 December 2018