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Webinar: Multicore RISC-V Designs in AI & Machine Learning Applications

06 May 2020 @ 4:00 pm-5:00 pm

Andes, Imperas, and UltraSoC hosted a webinar on how to easily optimize (including custom instructions and Vector, DSP extensions), accurately simulate, and precisely instrument, multicore RISC-V designs for AI Inferencing or ML applications.

The webinar was run twice on 6 May 2020, at 8am PDT (4pm BST, 5pm CET, 11pm CST) and 5pm PDT (1am BST, 2am CET, 8am CST on May 7).

Click here to access the webinar recording

The webinar covered the latest challenges’ designers are facing migrating AI/ML application to custom SoCs with RISC-V.

Artificial Intelligence (AI) and Machine Learning (ML) are among the fastest growing market segments as designers look to optimize domain specific SoC devices to accelerate complex algorithms and applications. While highlighting the latest examples for these applications many of the techniques and insights can equality be applied to any RISC-V based SoC design.

From a project perspective, the webinar covered the key stages of:

  • Architectural Exploration – Software driven prototype analysis with virtual platforms
  • Processor Core Configuration – Optimized features for Cores & Processor sub-systems
  • On-Chip Instrumentation – Debug & Trace, and On-Chip performance monitors

The webinar concluded with a hosted Q&A session with the presenters as a group discussion.