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Webinar – Optimizing complex AI and ML SoC designs: the role of system-level data
08 July 2021 @ 4:00 pm-4:45 pm
Please join us on Thursday 8 July at 4pm UTC+1 / 8am PST to find out how companies developing complex AI / ML SoCs can deploy functional data and analytics to meet demanding chip performance targets and validation schedules.
Hosted by Siemens Fellow Gajinder Panesar and Tessent Embedded Analytics Product Manager Richard Oxland, this new webinar will discuss the challenges of creating highly complex manycore AI / ML implementations, and show how system-level visibility of SoC functionality helps turn complexity into competitive advantage – in development, in validation, and throughout the deployed lifetime of the device.
What will you learn:
This webinar highlights the benefits of system-level visibility into the operation of complex, manycore chips for AI and ML computation tasks; and the value delivered by those functional insights, from chip validation through to deployment in the end application.
Who should join:
System-on-chip architects, verification engineers, validation engineers, embedded software architects and developers.
Can’t join us on the day?
Please do still register and a link to the recording will be sent to you.