At our second Cambridge RISC-V Meetup recently, around 60 delegates joined UltraSoC and Imperas Software, to discuss the latest updates on the RISC-V architecture and ecosystem.

In keeping with the theme of previous events, the talks were short and crisp to act as a catalyst for more in-depth conversations during the main social and networking activities over light refreshments. The engaging presentations covered a wide range of topics and touched on open source and commercial projects, hardware and software aspects, plus some activities within academia focused on RISC-V.

RISC-V state of the nation

UltraSoC CTO Gadge Panesar provided a ‘state-of-the-nation’ update from the RISC-V Foundation, as well as addressing some of the issues of systemic complexity posed by today’s typical heterogeneous SoC designs. While the core, or central CPU, is key to many aspects, it is all the details across the system integrations that are critical to overall performance and success in today’s demanding applications.

Open-source RISC-V tool chains

Jeremy Bennett, Embecosm CEO gave an interesting talk on ‘Open source RISC-V tool chains for professional software development’ and explained that most of the contributions to open source projects are actually professional engineers with ‘day-jobs’. Jeremy also gave an update on the latest RISC-V compilers with the GNU tool chain, LLVM and Plan 9.

Eliminating the gap between spec and implementation

Jonathan Woodruff from Cambridge University talked on the ‘TestRIG – Eliminating the test-gap between specification and implementation’ on behalf of the members of CTSRD from the University of Cambridge and University of Edinburgh. (CTSRD = Crash-worthy, Trustworthy, Systems Research & Development). Jon covered updates on the research into processor verification for architectural compliance and highlighted the merits of random test generation of instruction sequences and the work around formal models for RISC-V.

Modeling RISC-V with Sail

Alasdair Armstrong and Robert Norton-Wright presented ‘Modelling RISC-V with Sail’ as an update on CHERI (Capability Hardware Enhanced RISC Instructions). They started with the observation that ISA specifications are written as readable text so traditional designs suffer a pitfall from extensive documentation with potential for associated errors or ambiguity. RISC-V on the other hand starts with a clean and lean structure, so brevity is perhaps another advantage. Sail is a language for describing ISAs that with the advantages of machine readable allows for interesting options for verification.

UK Government champions security

John Goodacre of Innovate UK Knowledge Transfer Network and Digital Security by Design, Industrial Strategy talk was on ‘Overview and Introduction to UK Gov funded development for secure digital computing infrastructure’. John is an established figure within the Cambridge community and is well known to many of the audience. John gave his talk without slides, notes or a safety net and was a refreshing update on the latest program that the UK Government is funding to help stimulate industry and academic contributions to ensure future safeguards for security on embedded devices.

Designing and profiling RISC-V instructions

This was followed by a wide-ranging presentation from Imperas CEO Simon Davidmann who provided an update on compliance, progress on vector and bit manipulation instructions within RISC-V, and outlined a flow for designing and profiling RISC-V custom instructions and extensions.

These introduction talks helped stimulate some interesting conversations and discussions over the next couple of hours. As always catching up with colleagues old and new and first introductions to new contacts is best done over a beverage or two, and the discussions followed steadily as all aspects of RISC-V come up in some lively interactions across the group.

In the live technical demonstration session the UltraSoC team showcased the UltraSoC tools supporting debug and analysis of complex multi-core designs. In addition to RISC-V they walked through the challenges of heterogeneous designs and showed how system and SoC analytics needs to cover much more than just the CPU cores.


The Imperas demo table featured a live demo of the recently announced work with Google and Metrics within the new OpenHW group on verification of open source RTL cores. Based on the Google open source Instruction Stream Generator, the comparison between the RTL running on the Metrics cloud services and the Imperas reference model is expected to help verification for all RISC-V implementers and users, for both open source and commercial implementations.

If you missed the Meetup this time please join the Cambridge RISC-V Meetup Group to stay informed on forthcoming events and updates, and please contact us if you would like to participate in the future with a talk on a RISC-V related topic.

If you would like a copy of the slides presented during the RISC-V Meetup, please email

You can also read the blog posts from our previous RISC-V Meetup events in Bristol and Cambridge.