Kevin McDermott, VP Marketing with Imperas, attended DVCon Europe, where three RISC-V Foundation members give an introductory talk on the use of the industry’s leading open source instruction set architecture

DVCon Europe has evolved to become the region’s premier event for design test and verification. It brings together multiple disciplines including EDA vendors, systems and SoC developers with academic and industry experts. And not to forget: set in the wonderful city of Munich.

One of the highlights this year was a track on RISC-V, the open ISA which is rapidly growing interest across a range of markets and applications.

Three RISC-V Foundation members presented a RISC-V track.

An introduction to RISC-V

  • The architecture has successfully bridged from its academic roots to industry adoption
  • The RISC-V Foundation: more than 200+ members
  • Three key areas of Foundation activity – Technical, Security and Marketing – plus task groups in various areas
  • The work of the Compliance Working Group, aimed at ensuring RISC-V devices are a true representation of the specification and supporting the investment in software across the ecosystem

Presentation from Imperas

The presentation by Imperas focused on virtual platform, simulation, debug and analysis tools for an example use case for adding custom instructions to a RISC-V processor:

  • The need for compliance that addresses the various implementations of the RISC-V ISA
  • The ability to add and extend RISC-V with custom instructions
  • Profiling and analysis to optimize custom instructions for the target applications, including code coverage and testing

Presentation from Codasip

Codasip presented the complete design flow for RISC-V processor cores:

  • Automated tools and design flow for custom instructions
  • High-level abstraction description of processor IP
  • UVM verification flow

Presentation from UltraSoC

UltraSoC, which itself takes a leadership role in the Trace and Debug Working Groups, presented the on-chip analytics that:

  • Provide insight into device operation for debug and analytics
  • Monitor the interactions between heterogeneous processors
  • Collect data from a development board or from deployed device

Other tutorials and presentations at DVCon covered the latest developments around test and verification. Topics included Universal Verification Methodology (UVM), virtual prototyping, functional safety, transaction-level modeling (TLM), analog and mixed signal verification, advanced verification, stimulus generation, virtual platforms, visualization, and more.

In addition to the technical conference, the expo areas showcased 20 vendors of tools, solutions and services. With the food and beverage services close to hand the discussion and interactions covered the spectrum of the latest technical developments.

Plans are already in place for DVCon Europe 2019 and dates are expected to be announced shortly. For anyone looking to get an update on the latest industry trends and developments around test and verification, this will be a key event in 2019.