Following his attendance at the recent ORConf 2018, the open source conference in Gdansk, Poland, organized by FOSSi (The Free and Open Source Silicon Foundation), Marcin Hlond, Director Of System Engineering at UltraSoC shares his thoughts.

ORConf is described as the ‘open source digital design conference’, an annual event for open source digital, semiconductor and embedded systems designers and users. We were treated to a very lively and interactive meeting, more like a community gathering than a conference!

As the headline sponsor of the event, Western Digital brought a perspective on RISC-V, the open source CPU architecture it has committed to invest in and to help develop. Western Digital has already stated publicly that it plans to shift its own demand for cores (the company expects to be shipping in excess of 2 billion cores per year) to RISC-V – so clearly you would expect it to be out there singing the praises of RISC-V.

As you may know, UltraSoC also has a very active role in the RISC-V ecosystem. We play a central role in events around the world and work actively with a growing number of customers and partners covering the entire open source RISC-V ecosystem.

RISC-V obviously cropped up a lot at ORConf 2018  — the event was even co-sponsored by the RISC-V Foundation amongst others. Its progress since previous years was clear to see. The level of interest at ORConf, an event focused on open source design, confirmed what we’re witnessing every day in the wider market.

One of the valuable elements of events like this is finding out what’s really going on in the wider community, and it was exciting to hear about the progress the Pulp team (Bologna University) is making: they’ve gone some way down the line in developing complete systems based around open source RISC-V cores, for applications from IoT to high performance computing.

An interesting tangent from our perspective came from a discussion about open silicon manufacturing, making it easier to switch processes – but it could raise some serious questions about security. This is definitely an area in which UltraSoC’s analytics can bridge the gap to help make the open manufacturing process more secure: embedded intelligence can monitor not only performance and design parameters, but can also bring added reassurance and trackable insights to ensure security is not compromised.

What really stands out in my mind though was the theme that ran through a number of the ORConf sessions: how open source developments are able to support software teams to develop hardware.

One of the more interesting presentations came from VP Business Development at Antmicro Michael Gielda, and was entitled RISC-V & Renode: towards software-driven development. The Renode open source simulation framework was originally created for the development of software-driven embedded systems, but RISC-V’s popularity and growth now seems to be giving it fresh impetus and relevance. In an open ecosystem such as RISC-V, hardware and software co-development and simulation-driven workflows are a very natural fit.

We see an important role here for UltraSoC: embedding our analytics technology helps to monitor the design – giving the designer the added confidence in the performance and reliability of the entire system. At UltraSoC we’re keen to focus on the system more than the core. So whether it’s a single architecture RISC-V system, or – as we’re often witnessing – a heterogenous mixture of Arm, RISC-V and other cores, it is vital that the system is monitored and that the designer, software developer and even the end-user is aware of the interaction of every part of the system. For software teams designing hardware, the use of UltraSoC technology makes the process far more achievable and realistic by presenting them with a better understanding and greater insights into their design.

*Image of ORConf 2018 attendees courtesy of FOSSi Foundation