by Jo Windel | 15 July 2020
Optimizing embedded RISC-V hardware/software development from virtual models to in-life silicon instrumentation Join this webinar with Andes, Imperas, and UltraSoC on the use of virtual platforms and FPGA’s for RISC-V multicore SoCs as early development platforms and...
by Jo Windel | 25 June 2020
UltraSoC CTO Gajinder Panesar is looking forward to participating in the Munich RISC-V virtual meetup on 25 June 2020, 4pm to 6pm CEST. Alongside other presenters that include Western Digital, he will present on ‘On-Chip Instrumentation – Debug & Trace, and...
by Jo Windel | 06 May 2020
Andes, Imperas, and UltraSoC hosted a webinar on how to easily optimize (including custom instructions and Vector, DSP extensions), accurately simulate, and precisely instrument, multicore RISC-V designs for AI Inferencing or ML applications. The webinar was run twice...
by Jo Windel | 23 April 2020
Join us for the 2nd RISC-V meetup in Israel, hosted by Western Digital, UltraSoC and Codasip, to discuss RISC-V debug & trace infrastructure, unique paging techniques and SweRV Core™ support. The online event will be held on Thursday, April 23rd, 2020,...
by Rupert Baines | 22 January 2020
The past year has been an exciting one for UltraSoC. We’ve made significant progress in customer acquisition. We were honored that NSITEXE (part of the DENSO Group, the global automotive components manufacturer) featured us as part of their ecosystem at the recent...
