by Jo Windel | 19 June 2019
Following our successful first RISC-V Meetup in Cambridge last November, we are pleased to invite you to join us at our second one on Wednesday 19th June 2019, which will take place at Westminster College, Cambridge, and will be hosted by UltraSoC and Imperas...
by Annie Hudson | 21 June 2018
Advanced debug environment for multicore processor designs used for both hardware and simulation UltraSoC and Imperas today announced a wide-ranging partnership that will provide developers of multicore systems on chip (SoCs) with a powerful combination of embedded...
