RISC-V debug solutions
RISC-V is an open source instruction set architecture paving the way for the next 50 years of computing design and innovation.
In the five years prior to its recent acquisition by Mentor Siemens, UltraSoC has been a significant member of the RISC-V Foundation, deeply involved in developing and defining the debug architecture for RISC-V standards. The company fully supports both standards-based and proprietary debug approaches. UltraSoC was also the first to offer a RISC-V processor trace solution, supporting both open source and commercial processors including those from Andes, Codasip, Microchip, Roa Logic, SiFive and Syntacore.
Developing and supporting RISC-V debug standards
Tessent Embedded Analytics fully supports all of the major standards – both established and emerging – for RISC-V debug. And because we can monitor all major CPUs and custom logic, and perform protocol-aware probing of common buses, you can be certain that we can support you, and free you to make the best design choices for your SoC design.
You can read more about our RISC-V solutions by downloading our product brief.
For more information on RISC-V in general, including a presentation on debug by Gadge Panesar, visit the proceedings page of the 5th RISC-V workshop, which took place at Google’s Quad Campus in Mountain View, California.
Click here to download the RISC-V brochure
Click below to watch the RISC-V Demo
RISC-V Foundation Event Series
We support and regularly participate in the RISC-V Foundation event series.
RISC-V Summit 2019
We participated in the 2nd RISC-V Summit in San Jose (Dec 10-12) and demonstrated the industry’s only commercial debug and trace solution for RISC-V – as well as showed exciting developments that bring the potential of the RISC-V architecture to chip designers. Also, following hot on the heels of our announcement that we have joined the OpenHW Group, we announced some exciting news about our RISC-V trace solutions.
UltraSoC CTO Gajinder Panesar and VP Engineering Iain Robertson presented in the main program on ‘Every CPU Cycle Counts’. Also CEO Rupert Baines presented on the Western Digital booth, and Gajinder participated in a Processor IP Showcase panel session.
RISC-V Day Workshop Zurich
UltraSoC participated in the RISC-V Day Workshop Zurich in June 2019 and demonstrated its embedded analytics technology.
RISC-V China Roadshow
UltraSoC participated in the RISC-V China Roadshow in May 2019 which provided the chance to find out how to get started with RISC-V, via engaging presentations from Foundation members including UltraSoC, Alibaba, Andes and NXP, amongst many others.
RISC-V Workshop Taiwan
UltraSoC participated in the RISC-V Workshop Taiwan in early 2019 where delegates joined the expansive and international RISC-V ecosystem to discuss current and prospective RISC-V projects and implementations, as well as influence the future evolution of the instruction set architecture (ISA).
“UltraSoC continues to prove itself invaluable in helping Microsemi cement our leadership position in SoC development.
We’re committed to providing a complete solution for development teams looking to leverage the RISC-V architecture, in a broad range of applications. Working with UltraSoC reinforces and tangibly demonstrates that commitment to our customers.”
RISC-V processor trace now standardised: Even open source needs agreed specs
RISC-V processor trace spec is ratified
After eighteen months of hard work, it’s done: the RISC-V processor trace spec is ratified. This is excellent news and everyone involved should congratulate themselves on a job well done. You can find out more here. The RISC-V specifications, including Trace, are all available to view here.
UltraSoC donates RISC-V trace implementation to enable true open-source development
Works through OpenHW Group to support design innovation and ensure ecosystem compatibility
UltraSoC has announced it will offer an open-source implementation of its industry-leading RISC-V trace encoder via the OpenHW Group. The availability of a production-grade, standards-compliant processor trace solution is a key enabler for developers, and supports the OpenHW Group’s aim of creating an open, commercial grade ecosystem for development based on open-source processors.
Please click to read the full announcement
Webinar: Multicore RISC-V Designs in AI & Machine Learning Applications
Andes, Imperas and UltraSoC hosted a webinar that discussed the latest challenges’ designers are facing migrating AI/ML application to custom SoCs with RISC-V.
Artificial Intelligence (AI) and Machine Learning (ML) are among the fastest growing market segments as designers look to optimize domain specific SoC devices to accelerate complex algorithms and applications. While highlighting the latest examples for these applications many of the techniques and insights can equality be applied to any RISC-V based SoC design.
UltraSoC presents at Embedded World 2020
UltraSoC Marketing Director Andy Gothard presented on the RISC-V Foundation booth at Embedded World 2020 on ’21st Century designs need 21st Century tools: The case for embedded analytics’.
Click to watch the presentation
UltraSoC CTO and VP Engineering present at RISC-V Summit 2019
UltraSoC CTO Gajinder Panesar and VP Engineering Iain Robertson presented at the RISC-V Summit 2019 on ‘Every CPU Cycle Counts’. Also CEO Rupert Baines presented on the Western Digital booth, and Gajinder participated in a Processor IP Showcase panel session.
Click to watch the presentation
UltraSoC CEO presents at RISC-V Day Tokyo 2019
UltraSoC CEO Rupert Baines presented at the RISC-V Day Tokyo 2019 on ‘Embracing a system level approach in the real world: combining Arm and RISC-V in heterogeneous designs.’
To download the presentation please visit our Resources area.
Presentation: Processor Trace in a Holistic World
UltraSoC CTO Gajinder Panesar’s presentation at the 8th RISC-V Workshop in Barcelona outlined the importance of being able to debug in a holistic manner; to make the move to RISC-V as seamless as possible there needs to be an eco-system beyond the core itself.
“The fact that UltraSoC, as a focused commercial IP supplier, is donating its trace hardware, sends a signal that the open-source hardware movement is gathering pace and maturing. Processor trace is a key technology for developers using open-source CPUs: having access to a standards-compliant RISC-V trace solution is a major contribution in our quest to create a comprehensive ecosystem that delivers robust, commercial grade open-source platforms.”
“The N25 and NX25 AndesCore processors are selected by our customers for their exceptional performance/power, flexible configurations, and comprehensive development tools. Choosing UltraSoC as our preferred partner for embedded analytics, trace and validation gives our customers an advanced development environment with insight into SoC operations and processor execution without disturbing target behaviour.
UltraSoC has shown itself to be committed to the development of the RISC-V ecosystem and hence it is clearly the best partner for our V5 RISC-V architecture. We are delighted to already be engaged with multiple mutual customers using Andes processor N25/NX25 with UltraSoC’s IP and trace solution to address their demanding applications.”
“Esperanto’s goal is to make RISC-V the architecture of choice for the most demanding AI and machine learning applications,” said Dave Ditzel, Founder and CEO of Esperanto. “UltraSoC’s IP will help our users see complex interactions between processors so they can understand what is going on and how to optimize performance better. Developing and debugging software utilizing thousands of RISC-V cores will be easier with the advanced analytics that UltraSoC’s IP will provide.”
“The use of heterogeneous architectures is growing rapidly, and the rise of RISC-V shows that more than ever, designers don’t want to be restricted in their architectural choices.
Our existing relationship with UltraSoC demonstrates the power of combining our respective sets of vendor-independent development tools – giving our customers the ability to choose both the IP they use in their chip, and the environment in which they develop and debug.”