RISC-V debug solutions
The industry’s leading standards-compliant debug and trace solutions for RISC-V
Embedded Analytics allows silicon development teams to rapidly debug, validate and optimize their products with the industry’s leading standards-compliant debug and trace solution for RISC-V systems. Our silicon IP (RTL) and software offers a complete range of features, from basic processor run-control to sophisticated cycle-accurate processor tracing, enabling:
- Traditional run-halt debug
- Visualization of real-time hardware / software behavior in a single software tool
- Support for any compliant RISC-V core, including custom instructions
- Forensic debug and root-cause analysis
- Identification and analysis of infrequent and random bugs
- Non-intrusive analysis of “Heisenbugs”
- Code profiling
- Code coverage
Publicly announced customers and partners for our RISC-V offering include Andes, Codasip, Esperanto, Lauterbach, Microchip, Picocom, Seagate and Western Digital, to name but a few. Find out more by downloading our RISC-V Solution brief
“Software engineers can’t perfect what they can’t observe. They need tools that offer full visibility of code execution in real-time, to allow them to optimize SoC performance, reduce costs and speed time-to-market”
Efficient trace for RISC-V
At the heart of the Embedded Analytics RISC-V solution is our trace encoder, an RTL module which can capture, efficiently encode and transmit off-chip a record of executed instructions from any standards-compliant RISC-V CPU. Processor trace enables you to reconstruct the exact execution sequence of your program, inspect timing-sensitive phenomena and analyze how the software is interacting with the chip’s hardware. In addition to implementing all of the mandatory and optional features of the RISC-V E-Trace standard, we provide unique cycle-accurate and data trace options to give you the most intimate understanding of code execution. And we fully support the custom instruction capabilities of the RISC-V ISA.
Having donated the original processor trace specification to the community, we formally announced RISC-V processor trace support in 2017, and delivered our first generation trace encoder in January 2018. Since then we have added leading-edge features such as out-of-order execution, data trace, superscalar operation and cycle-accurate tracing – as well as maintaining full compliance as the E-Trace standard has emerged and evolved.
Embedded Analytics: beyond processor trace
We support our RISC-V trace solution with a range of hardware modules and software that dramatically ease the architecture and design teams’ task of debug infrastructure integration, while also offering the debug and validation team a powerful feature set and unprecedented flexibility.
- Our efficient, message-based on-chip communications scheme allows a natural bottom-up, subsystem-based design approach and eases timing closure, while enabling run-time configuration of cross-triggering.
- We can integrate gracefully with common debug architectures such as Arm Coresight
- We provide hardware support for a wide range of external interfaces including JTAG and USB
- Our DMA module, USB communicator and supporting software allow you to efficiently upload software to the target system, and to examine system memory content during execution
- You can choose our Eclipse-based SystemInsight tool or a third-party debugger such as Lauterbach Trace32 or Ashling RiscFree
A path to system-level debug solutions
RISC-V E-Trace from Embedded Analytics provides the most efficient processor trace and debug solution around. But today’s SoCs often require more than a processor-centric view. Embedded Analytics provides a complete range of silicon IP (RTL), APIs/libraries, software applications and verification IP, enabling a system-level approach to debug, hardware/software validation, and SoC performance optimization. In addition to our SystemInsight debugger, we provide Python-based scripting extensions that allow you to make use of data from the full range of Embedded Analytics hardware monitors. These powerful facilities allow you to take on the most complex debug and optimization tasks and employ advanced techniques:
- High-bandwidth memory controller (HBM) optimization
- Analysis of multi- and many-core systems (including those using multiple CPU ISAs, DSPs and accelerators)
- Self-hosted or “monitor mode” debug
- Transaction-level analysis of interconnect performance
Join our RISC-V webinar
and find out how E-Trace from Siemens can help your RISC-V deployment
Our history in
Our involvement in RISC-V goes back to 2016 and the earliest days of the RISC-V Foundation (now RISC-V International). In the years since then, initially as UltraSoC, subsequently as Mentor and now as Siemens EDA, we have made active and extensive contributions to the development of the RISC-V ecosystem. These have included key technical contributions to the RISC-V Efficient Trace (E-TRACE) standard, and continue today through the involvement of Iain Robertson, our Senior Director of Hardware Operations and Engineering, as Chair of the RISC-V Debug Trace and Performance Monitoring SIG.
Why choose E-Trace?
In 2018, the RISC-V community took the visionary decision to build its processor trace specification from the ground up. The aim was not just to ensure compatibility across the RISC-V ecosystem, but also to adopt an efficient encoding scheme fit for the needs of processors in the 21st Century. Trace generates lots of information: an efficient coding scheme allows you to trace for longer time periods, reduces trace memory buffer requirements, avoids trace loss due to backpressure, and reduces bandwidth requirements on the off-chip transport system.
RISC-V E-Trace provides the most efficient solution for all of these requirements, allowing you to understand program behavior, even in the most complex multicore systems.