IP Modules

Tessent Embedded Analytics provides a suite of semiconductor IP that allows chip designers to integrate an intelligent analytics infrastructure into the core hardware of their devices. By monitoring the real-world behavior of entire systems and analyzing those insights with appropriate software – running on- or off-chip – engineers can take action to reduce system power consumption, increase performance, protect against malicious intrusions, and ensure product safety.

Scroll down or click to read more about our four categories of Tessent Embedded Analytics IP modules

Analytic Modules
Secure Message Infrastructure
Communicators
Active Managers

 

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Shortform descriptions of our silicon IP, including analytic modules, message infrastructure and communicators.

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Analytic Modules

Direct and indirect coupling of the PAM

Bus Monitor
The Bus Monitor provides complete, transaction-level visibility of SoC bus activity across all major bus standards, including AXI, ACE and OCP. With a wide variety of monitoring functions it can be used for analytics, reporting diagnostics, performance profiling and other applications.

Direct Memory Access (DMA)
The DMA analytic module provides direct memory access. It enables an external application to issue transactions on the bus fabric in order to read or write a block of memory. This module enables program loading in a Tessent Embedded Analytics system as well as direct memory inspection via read accesses and manipulation via write accesses.

GPIO Trigger Module
The GPIO Trigger Module can be used to connect the Tessent Embedded Analytics infrastructure to other parts of the system in order to provide event and configuration functions such as: Event inputs, Event Outputs, GPIO. Its input event interface can be used to initiate real-time events and/or Tessent Embedded Analytics messages on the outgoing message interface.

Network on Chip Monitor
The Tessent Embedded Analytics NoC Monitor provides complete, transaction-level visibility of SoC bus activity for devices using the Arm® AMBA® 5 Coherent Hub Interface (CHI). The NoC Monitor can be used for analytics, reporting diagnostics and performance profiling and supports the need for fast, non- blocking data transfers between multiple fully coherent processors within an SoC.

Processor Analytic Module
Processor Analytic Modules couple processors or their processor specific debug port to the Tessent Embedded Analytics system. They are intended to control the processor core, extract processor related status information and performance data as well as integrate with the processor’s existing debug support which may additionally provide instruction and or data trace.

Static Instrumentation
Tessent Embedded Analytics Static Instrumentation equips embedded software developers with a non-intrusive mechanism for code instrumentation. Using the Static Instrumentation module, the developer can insert watchpoints in the code that trigger messages on the Tessent Embedded Analytics subsystem, with minimal impact on the execution flow.

Status Monitor
The Tessent Embedded Analytics Status Monitor gives access to the signaling lines of custom logic within an SoC. It affords many of the benefits of a logic analyzer, but with no need to bring signals off-chip. The Status Monitor enables the design verification and performance monitoring of custom logic, all embedded within the chip. It provides a wide variety of functions including debugging, reporting diagnostics, and performance profiling.

System Memory Buffer
The System Memory Buffer communicator provides a way to buffer and store messages in a region of shared system memory. It provides a capability to store messages received on its input message interface to an area of system memory.

Trace Encoder
The RISC-V Trace Encoder provides a mechanism to monitor the program execution of a CPU in real time. It encodes instruction execution and, optionally, data memory accesses, and outputs data in a highly compressed format. Software running externally can take this data and use it to reconstruct the program execution flow.

Trace Receiver
The Trace Receiver module accepts trace data, typically generated by a CPU, and encapsulates it into Tessent Embedded Analytics messages to be transferred off-chip via the Tessent Embedded Analytics infrastructure. As well as allowing the use of versatile and high-bandwidth interfaces such as USB to extract trace, this module is also capable of incorporating any vendor’s triggering mechanisms into a Tessent-enabled system; this enables powerful cross-triggering across a heterogeneous SoC.

Virtual Console
The Virtual Console analytic module provides a peripheral interface that enables the system software to communicate with an external host via the Tessent Embedded Analytics infrastructure. The Virtual Console is intended to replace a conventional UART based communication within systems that require console connections, such as standard I/O (for example, printf) and those with operating systems and application tasks that can be configured or interacted with via a serial terminal dialogue.

 

Secure Message Infrastructure

Secure Message Infrastructure
The Secure Message Infrastructure (SMI) interconnects Tessent Embedded Analytics on-chip monitors, communicators and Sentries, enabling SoC designers to create system-wide analysis, optimization and security implementations. The SMI is a secure, scalable communications fabric independent from the main SoC interconnect, which allows messages, control signals and trace data to be routed between on-chip modules and to external software and hardware resources.

 

 

 

 

Communicators

Interfacing the EBC Communicator

Bus Communicator (AXI)
The AXI Bus Communicator enables software running inside the chip to drive the Tessent Embedded Analytics system as an intelligent analytics agent through a bus slave such as AXI or similar. This allows on-chip software to monitor itself during pre-deployment soak- testing and carry out performance optimization throughout the product life. The Bus Communicator enables monitoring of critical software and on-chip activity using either background software on the applications processor or a smaller processor core dedicated to housekeeping activities.

USB Communicator
The USB 2.0 Communicator provides medium-speed debug access to the Tessent Embedded Analytics system for an off-chip debugger or analytics API over USB. Offered as a USB device, or compound USB hub and device, the USB Communicator is intended for direct connection to a USB PHY interface to enable a dedicated debug channel or to the optional Tessent Embedded Analytics USB debug hub core.

EBC communicator
The EBC Communicator provides high-speed communications from a Tessent Embedded Analytics system to an off-chip debugger or analytics API via USB3. It provides an AXI Slave Interface along with a set of sideband signals to be connected to a DMA Master, such as a USB3.1 Controller, to provide high bandwidth output from the Embedded Analytics Infrastructure.

JTAG Communicator
The JTAG Communicator provides low-bandwidth connectivity to the Tessent Embedded Analytics infrastructure via an IEEE 1149.1 scan-test interface. The JTAG Communicator implements a simple link-layer protocol above the physical layer signaling defined by the IEEE 1149.1 standard.

Trace Communicator
The Trace Communicator provides a way to drive Tessent Embedded Analytics messages into an alternative debug system or external parallel port. It enables a Tessent system to be interfaced with the trace functionality offered by several CPU vendors.

 

Active Managers

Security in hardware

Bus Sentry
The Bus Sentry can be used as the core of a hardware-based on-chip security system. The Bus Sentry allows SoC designers to control access to sensitive areas of their devices, detect and block suspicious transactions at hardware speed, and build a long-term profile of system operation to secure against current and future cyber threats.

Lockstep Manager
The Lockstep Manager is a configurable, hardware-based, scalable solution that can be used to verify the operation of two or more on-chip hardware subsystems, including CPUs, hardware accelerators or custom logic blocks. It supports all common lockstep/redundancy architectures, including full dual-redundant lockstep, master/checker, and voting with multiple cores or subsystems.