Works through OpenHW Group to support design innovation and ensure ecosystem compatibility
UltraSoC today announced it will offer an open-source implementation of its industry-leading RISC-V trace encoder via the OpenHW Group. The availability of a production-grade, standards-compliant processor trace solution is a key enabler for developers, and supports the OpenHW Group’s aim of creating an open, commercial grade ecosystem for development based on open-source processors.
Rupert Baines, CEO of UltraSoC, said: “We fully believe in industry standards and the importance of open-source; by donating this encoder we can help industry adoption of RISC-V, strengthen the ecosystem and support compatibility and consistency. Open-source is a familiar model in the software world, but in hardware we’re just beginning to unlock the possibilities of this powerful approach. The RISC-V ISA has provided initial momentum, and industry bodies such as the OpenHW Group are now taking it a step further. At the same time, the legal framework has developed to allow hardware IP companies to confidently license their technologies.”
Rick O’Connor, CEO of the OpenHW Group, commented: “The fact that UltraSoC, as a focused commercial IP supplier, is donating its trace hardware, sends a signal that the open-source hardware movement is gathering pace and maturing. Processor trace is a key technology for developers using open-source CPUs: having access to a standards-compliant RISC-V trace solution is a major contribution in our quest to create a comprehensive ecosystem that delivers robust, commercial grade open-source platforms.”
The open-source RISC-V trace solution will be fully compatible with the processor trace standard currently being developed within the RISC-V Foundation’s Processor Trace Working Group. UltraSoC developed the original RISC-V trace encoding algorithm in 2016, donating the specification as open-source shortly afterwards; pre-standard implementations of the specification are already shipping. The company has been a leading contributor to the RISC-V Foundation since 2016: its CTO, Gajinder Panesar, co-chairs the Processor Trace group.
The open-source implementation, which will be available at the end of Q1 2020, includes the core functionality expected to be included in the standard: users can upgrade to UltraSoC’s full commercial offering, giving them access to additional sophisticated features such as multiple retirement, out-of-order trace, cycle-accurate tracing, and the filters and counters required for more complex performance analysis. The commercial offering is fully consistent with UltraSoC’s range of monitoring and analytics tools, enabling not just development but optimization and cybersecurity applications.
The company will provide further support for the open-source version by offering evaluation-style licensing of its UltraDevelop tool suite, which provides an Eclipse-based environment in which behavioral data from any chip can be captured and visualized. The hardware deliverable is product-quality/commercial grade and also includes test benches and verification tests.
UltraSoC’s embedded analytics technology allows monitoring and analysis of the behavior of almost any on-chip structure, including CPUs, interconnects / NoCs and even custom logic. Its monitoring architecture gives the system architect free choice over which third-party IP to acquire, which parts of the design need to be custom coded, and how to interconnect the system. This “open” approach to its commercial offering is now reflected in the availability of a commercial grade open-source tool for processor trace and debug.
Established early in 2019, the OpenHW Group has grown rapidly over recent months. Its CORE-V processors are commercial-quality RISC-V based cores offered on an open-source basis, with associated processor subsystem IP, tools and software. The IP is available in both silicon and FPGA optimized implementations. These cores can be used to facilitate rapid design innovation and ensure effective manufacturability of high-volume production SoCs.