New IP extends UltraSoC’s family of protocol-aware monitors for interconnect to ARM AMBA-5 CHI
CAMBRIDGE, UK, 26th October 2016: UltraSoC today extended the capabilities of its on-chip monitoring and analytics semiconductor intellectual property (IP), to include debug, monitoring and analysis features for the ARM® AMBA® 5 Coherent Hub Interface (CHI). The CHI Monitor is the newest in UltraSoC’s family of protocol-aware monitors for interconnect and extends that from bus monitors to debugging and fine-tuning the NoC (network on chip) fabric.
CHI supports the increasing need for fast, non-blocking data transfers between multiple fully coherent processors within a system-on-chip (SoC), with the goal of ensuring efficient use of critical on-chip blocks and hence improving quality of service across the device. UltraSoC’s new CHI NoC Monitor module permits detailed real-world monitoring and analysis of the functioning of the interconnect, allowing chip developers to fine-tune its performance and optimize overall SoC performance. It is the latest member of UltraSoC’s portfolio of components for giving visibility and understanding of the behavior and operation of SoCs.
“UltraSoC’s goal is to provide benefits across the SoC and throughout the development flow,” said Gadge Panesar, UltraSoC CTO. “On-chip interconnects are vital to the performance of a SoC: understanding and optimizing their performance to prevent bottlenecks is a major part of that effort, particularly in high-performance cache-coherent designs. For that reason, UltraSoC’s comprehensive range of silicon IP includes Bus Monitors, Status Monitors and sophisticated scriptable analytics facilities. CHI is itself targeted at higher performance SoCs, so the need for a credible monitoring, analytics and debug solution is critical.”
“A key strength of the ARM ecosystem is that many independent companies can develop their own IP that builds on a shared platform, enabling the creation of unique and innovative features,” said Nandan Nayampally, vice president of marketing and strategy, CPU Group, ARM. “UltraSoC’s protocol-aware monitors allow customers a better insight into the operation of the SoC, a benefit that becomes particularly important as SoCs continue to grow in complexity with cache-coherent designs.”
UltraSoC accelerates chip development cycles, improves product quality and reduces risk by providing a holistic, chip-wide debug architecture that allows system-level performance monitoring that is IP vendor independent.
The CHI NoC Monitor complements UltraSoC’s family of Bus Monitors, supporting non-intrusive “smart” analytics of standard interconnects including AXI, ACE, ACE-lite, OCP and others. These enable full visibility of traffic on buses with a range of measurements, analytics and statistics gathering. The supported metrics include: transactions; bus cycles; latency; duration; bytes; beats; bus concurrency and trace. All of these are highly configurable and include “logic analyzer” style controls and dependencies, local buffering and cross-triggering. In addition, the modules can track transactions, such as trace, and automatically gather statistics to identify issues such as contention, peak traffic, and deadlock.
As well as allowing debug and performance monitoring, UltraSoC’s suite of silicon IP facilitates the creation of value-add on-chip features such as hardware-based security capabilities (Bare Metal Security™) and end-product performance optimization. It provides benefits not just to silicon design teams, but also to software developers and system integrators. It enables non-intrusive, wire-speed monitoring of a chip’s real-world behavior, giving engineers an intimate understanding of the complex interactions between diverse on-chip processor blocks, custom logic and system software.