CAMBRIDGE, United Kingdom, 20th September 2016
UltraSoC, the leading provider of semiconductor IP for on-chip analytics, performance optimization and hardware-based security, today announced that it will provide support within its universal system-on-chip (SoC) debug solution for products based on the RISC-V open-source instruction architecture (ISA). The company also lent its support to the RISC-V Foundation, the non-profit corporation that directs the development and drives the adoption of the RISC-V ISA, which many observers believe will evolve to be “the Linux of the semiconductor industry”.
RISC-V was originally designed to support computer architecture research and education, but as concern has grown in the industry about the increasing dominance of one or two proprietary microprocessor architectures, the RISC-V ISA has aroused interest as a potential open architecture for commercial use. A strong development and debug infrastructure is essential to the success of any chip architecture, and UltraSoC’s vendor-neutral, partnership-based approach perfectly complements the RISC-V open ISA principles.
“RISC-V has attracted the interest of leaders like Google and HP,” said David Kanter of The Microprocessor Report. “The open-source nature of RISC-V is novel, and gives many companies a new opportunity to innovate with specialized hardware components for emerging applications. As with any processor architecture, the RISC-V ISA needs many complementary software and hardware elements to create a full solution. Advanced, vendor-neutral development, debug and analytics support is essential. As such, the participation of specialist firms like UltraSoC is an important step for the RISC-V community”.
“We are delighted to welcome UltraSoC to the RISC V community,” said Rick O’Connor, Executive Director of the RISC V Foundation. “With the Foundation we are building a complete eco-system: end users, processor architects, tools vendors and supporting components. UltraSoC’s debug and development tools will be a great addition to the community.”
UltraSoC’s silicon IP and software tools will provide the RISC-V community with secure, independent on-chip capabilities that non-intrusively monitor and analyze the device’s internal behavior. These powerful features speed development and reduce risk for chip designers both pre- and post-silicon. They ease the often complex task of writing and debugging software for complex devices, and allow robust hardware-based security features that can detect unexpected behavior caused by bugs or by malicious interference (Bare Metal Security™). UltraSoC is compatible with open-source design automation tools such as GDB, as well as a wide variety of commercial third-party products from leaders such as Lauterbach and Teledyne LeCroy.
”We’re delighted to be able to support RISC-V, and we’re committed to doing whatever we can to make it a success,” said Rupert Baines, UltraSoC CEO. “Our stance is vendor neutral and ecosystem based. We aim to create a universal development and debug infrastructure in which designers can freely choose the best architecture for the job – and mix and match their own IP with in-house blocks to create uniquely differentiated products. I believe our approach is an excellent fit with the aims and aspirations of the RISC-V movement.”
About the RISC-V Foundation
RISC-V (pronounced “risk-five”) is a new instruction set architecture (ISA) that was originally designed to support computer architecture research and education and is now set to become a standard open architecture for industry implementations under the governance of the RISC-V Foundation. The RISC-V ISA was originally developed in the Computer Science Division of the EECS Department at the University of California, Berkeley.
The RISC-V Foundation, a non-profit corporation controlled by its members, directs the future development and drives the adoption of the RISC-V ISA. Members of the RISC-V Foundation have access to and participate in the development of the RISC-V ISA specifications and related HW / SW ecosystem. For more information visit http://www.riscv.org